Secure and Trustworthy Hardware (SETH) Lab

Publications

Books
Patents
Book Chapters
Journals
Conferences

Books

M. Yasin, J. Rajendran, and O.Sinanoglu, Trustworthy Hardware Design: Combinational Logic Locking Techniques, Springer, 2019. Link

 

 

 

 

 

 

Patents

  1. J. Rajendran, O. Sinanoglu and R. Karri, System, Method And Computer-Accessible Medium For Fault Analysis Driven Selection Of Logic Gates To Be Camouflaged, U.S. Patent pending, filed Sep 2013.
  2. J. Rajendran, Y. Pino, R. Karri and O. Sinanoglu, System, Method and Computer-Accessible Medium for Facilitating An Unbreakable Logic Encryption, U.S. Patent pending, filed Mar, 2013.
  3. J. Rajendran, O. Sinanoglu and R. Karri, System, Method and Computer-Accessible Medium for Providing Secure Split Manufacturing, U.S. Patent pending, filed Mar, 2013.
  4. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Systems, processes, and computer-accessible medium for providing Logic Encryption using Fault analysis, U.S. Patent pending, filed Jan, 2012.
  5. V. Jyothi, R. Karri, J. Rajendran, and O. Sinanoglu, Reconfiguring functional path into Trojan detecting Ring oscillators, U.S. Patent pending, filed March, 2011.

Book Chapters

  1. M. Yasin, B. Mazumdar, J. Rajendran, and O. Sinanoglu, Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution. In: The IoT Physical Layer. Springer, 2019.
  2. R. Karri, J. Rajendran, and K. Rosenfeld, Trojan Taxonomy. In: Hardware Security and Trust, Pages 325-338, 2012.

Journals

  1. R.Kande, H. Pearce, B. Tan, B. Gavitt, S. Thakur, R. Karri, and J. Rajendran, (Security) Assertions by Large Language Models, in IEEE Transactions on Information Forensics and Security, 2024
  2. V. Gohil, S. Patnaik, H. Guo, D. Kalathil, and J. Rajendran, DETERRENT: Detecting Trojans Using Reinforcement Learning, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.43, no. 1, pp. 57-70, 2024.
  3. V. Gohil, M. Tressler, K. Sipple, S. Patnaik, and J. Rajendran, Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing, in IEEE Transactions on Information Forensics and Security, vol. 16, pp. 5077-5092, 2021
  4. N. G. Jayasankaran, A. Sanabria Borbon, E. Sánchez-Sinencio, J. Hu, and J. Rajendran. Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction, IEEE Transactions on Emerging Topics in Computing, pp. 1-8, 2020.
  5. N. G. Jayasankaran, A. Sanabria Borbon, A. Abuellil, E. Sánchez-Sinencio, J. Hu, and J. Rajendran. Breaking Analog Locking Techniques, IEEE Transactions on Very Large Scale Integration Systems, Pages 1-14, 2020.
  6. A. Chakraborty, N. G. Jayasankaran, Y. Liu, J. Rajendran, A. Srivastava, O. Sinanoglu, Y. Xie M. Yasin, and M. Zuzak. Keynote: A Disquisition on Logic Locking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-21, 2019.
  7. C. Yang, B. Liu, H. Li, Y. Chen, M. Barnell, Q. Wu, W. Wen, and J. Rajendran. Thwarting Replication Attack against Memristor-based Neuromorphic Computing System, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-14, 2019.
  8. Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran. The Cat and Mouse in Split Manufacturing, IEEE Transactions on VLSI Systems, Volume 26, Issue 5, Pages: 805-817, 2018.
  9. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran. Removal Attacks on Logic Locking and Camouflaging Techniques, in IEEE Transactions on Emerging Topics in Computing, pp. 1-16, 2017.
  10. M. Yasin, O. Sinanoglu, and J. Rajendran. Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging, in IEEE Transactions on Information Forensics and Security 12, no. 11 (2017): 2668-2682.
  11. S. Ali, M. Ibrahim, J. Rajendran, O. Sinanoglu, and K. Chakrabarty. Supply-Chain Security of Digital Microfluidic Biochips, IEEE Computer Magazine, Volume 49, Issue 8, Pages 36-43, 2016.
  12. S. E. Zeltmann, N. Gupta, N. Tsoutsos, M. Maniatakos, J. Rajendran, and R. Karri. Manufacturing and Security Challenges in 3D printing, Journal of Materials, Volume 68, Issue 7, Pages 1872-1881, 2016. (Most read paper in Springer Engineering in 2016)
  13. J. Rajendran, O. Sinanoglu, and R. Karri. Building trustworthy systems using untrusted components: A High-level synthesis approach, IEEE Transactions on Very Large Scale Integration Systems, Volume 24, Issue 9, Pages 2946-2959, 2016.
  14. M. Yasin, J. Rajendran, O. Sinanoglu, and R. Karri. On Improving the Security of Logic Locking, IEEE Transactions on Computer-Aided Design, Volume 35, Issue 9, Pages 1411-1424, 2015.
  15. J. Rajendran, A. Ali, O. Sinanoglu, and R. Karri. Belling the CAD: Towards Security-Centric Electronic System Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34, Issue 11, Pages 1756-1769, 2015.
  16. J. Rajendran, Ramesh Karri, James B.Wendt, Miodrag Potkonjak, Nathan McDonald, Garrett S. Rose, and Bryant Wysocki. Exploring Nanoelectronic Devices for Security Applications, IEEE, Volume 103, Issue 5, Pages 829-849, 2015.
  17. J. Rajendran, R. Karri, and G.S. Rose. Improving Tolerance to Variations in Memristor-based Applications Using Parallel Memristors, IEEE Transactions on Computers, Volume 64, Issue 3, Pages 733-746, 2015.
  18. J. Rajendran, H. Zhang, C. Zhang, G.S. Rose, Y. Pino, O. Sinanoglu, and R. Karri. Fault Analysis-based Logic Encryption, IEEE Transactions on Computers, Volume 64, Issue 2, Pages 410-424, 2015. (Popular paper in IEEE Transactions on Computers, Nov. 2016)
  19. Chen Liu, J. Rajendran, Chengmo Yang, and Ramesh Karri. Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling, IEEE Transactions on Emerging Topics in Computing, Volume 2, Issue 4, Pages 461-472, 2014.
  20. J. Rajendran, O. Sinanoglu, and R. Karri. Regaining Trust in VLSI Design: Design-for-Trust Techniques, IEEE, Volume 102, Issue 8, Pages 1266-1282, 2014.
  21. J. Rajendran, A. K. Kanuparthi, M. Zahran, S. Addepalli, G. Ormazabal, and R. Karri. Securing processors against insider attacks: a circuit-microarchitecture co-design approach, IEEE Design and Test Magazine (Special Issue on Trusted SoC with Untrusted Components), Volume 30, Issue 2, Pages 35-44, 2013.
  22. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri. Sneak Path Testing of Crossbar-based Non-volatile Random Access Memories, IEEE Transactions on Nanotechnology, Volume 12, Issue 3, Pages 413-426, 2013.
  23. J. Rajendran, H. Manem, R. Karri, and G.S. Rose. An Energy-Efficient Memristive Threshold Logic Circuit, IEEE Transactions on Computers, Volume 61, Issue 4, Pages 474-487, 2012.
  24. G.S. Rose, H. Manem, J. Rajendran, R. Karri, and R. Pino. Leveraging Memristive Systems in the Construction of Digital Logic Circuits, IEEE, Volume 100, Issue 6, Pages 2033-2049, 2012.
  25. H. Manem, J. Rajendran, and G.S. Rose. Design Considerations for Multi-Level CMOS/Nano Memristive Memory, ACM Journal of Emerging Technologies in Computing, Volume 8, Issue 1, Pages 6:1-6:22, 2012.
  26. H. Manem, J. Rajendran, and G.S. Rose. Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array, IEEE Transactions on Circuits and Systems-I, Volume 59, Issue 5, Pages 1051-1060, 2012.
  27. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J. Rajendran, and K. Rosenfeld. Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges, Computer Magazine, Volume 44, Issue 7, Pages 66-74, 2011.
  28. R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor. Trustworthy Hardware: Identifying and Classifying Hardware Trojans, Computer Magazine, Volume 43, Issue 10, Pages 39-46, 2010.

Conferences

  1. Matthew DeLorenzo, Vasudev Gohil, and Jeyavijayan (JV) Rajendran. CreativeEval: Evaluating Creativity of LLM-Based Hardware Code Generation, accepted at IEEE International Workshop on LLM-Aided Design, 2024.
  2. Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, and Jeyavijayan (JV) Rajendran. AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning, accepted at USENIX Security Symposium, 2024. Source code and artifacts
  3. Pallavi Borkar*, Chen Chen*, Mohamadreza Rostami, Nikhilesh Singh, Rahul Kande, Ahmad-Reza Sadeghi, Chester Rebeiro, and Jeyavijayan (JV) Rajendran. WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors, accepted at USENIX Security, 2024. (* indicates equal contribution)
  4. Jonathan Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, Jeyavijayan Rajendran and Yiran Chen. ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM, accepted at IEEE/ACM Design Automation Conference (DAC), 2024.
  5. Mohamadreza Rostami, Shaza Zeitouni, Rahul Kande, Chen Chen, Pouya Mahmoody, Jeyavijayan Rajendran and Ahmad-Reza Sadeghi. Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection, accepted at IEEE/ACM Design Automation Conference (DAC), 2024.
  6. Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, and Ahmad-Reza Sadeghi. Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing, in IEEE Design, Automation and Test in Europe Conference, 2024.
  7. Vasudev Gohil*, Rahul Kande*, Chen Chen, Ahmad-Reza Sadeghi, and Jeyavijayan (JV) Rajendran. MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors, in IEEE Design, Automation and Test in Europe Conference, 2024. (* indicates equal contribution)
  8. Peng-Hao Huang, Jaewon Kim, P. R. Kumar, Jeyavijayan Rajendran, and Prasad Enjeti. Enhancing Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-dependent Industrial Infrastructures, in IEEE Energy Conversion Congress & Expo Conference, 2023.
  9. Chen Chen*, Vasudev Gohil*, Rahul Kande, Ahmad-Reza Sadeghi, and Jeyavijayan (JV) Rajendran. PSOFuzz: Fuzzing Processors with Particle Swarm Optimization, in IEEE/ACM International Conference on Computer-Aided Design, pp. 1-9, 2023. (* indicates equal contribution)
  10. Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa Shihab, Yiorgos Makris, Jeyavijayan (JV) Rajendran. FuncTeller: How Well Does eFPGA Hide Functionality?, in USENIX Security, pp. 1-18, 2023.
  11. Chen Chen, Rahul Kande, Nathan Nguyen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, and Jeyavijayan (JV) Rajendran. HyPFuzz: Formal-Assisted Processor Fuzzing, in USENIX Security, pp. 1-19, 2023. Source code.
    CVEs reported: CVE-2022-33021, CVE-2022-33023
  12. Hao Guo, Sayandeep Saha, Vasudev Gohil, Satwik Patnaik, Debdeep Mukhopadhyay, and Jeyavijayan (JV) Rajendran. ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning, in Design Automation Conference, pp. 1-6, 2023.
  13. Vasudev Gohil, Hao Guo, Satwik Patnaik, and Jeyavijayan (JV) Rajendran. ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning, in ACM SIGSAC Conference on Computer and Communications Security (CCS), pp. 1-20, 2022. Source code and artifacts.
  14. Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan (JV) Rajendran, and Ankur Srivastava. Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool (Invited Paper), in IEEE/ACM International Conference on Computer-Aided Design, pp. 1-8, 2022.
  15. Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, and Jeyavijayan Rajendran. DETERRENT: Detecting Trojans using Reinforcement Learning, in Design Automation Conference, pp. 1-7, 2022. Source code and artifacts.
  16. Rahul Kande, Addison Crump,  Garrett Persyn, Patrick Jauernig, Ahmad-Reza Sadeghi, Aakash Tyagi, and Jeyavijayan Rajendran. TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities, in USENIX Security, pp. 1-19, 2022. Source code.
    CVEs reported: CVE-2021-40506, CVE-2021-40507, CVE-2021-41612, CVE-2021-41614, CVE-2021-41613
  17. Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande. Organizing The World’s Largest Hardware Security Competition: Challenge, Opportunities, and Lessons Learned., in GLSVLSI, pp. 95-100, 2021.
  18. Zhaokun Han, Muhammad Yasin, and Jeyavijayan Rajendran. Does Logic Locking work with EDA tools?, in USENIX Security, pp. 1-19, 2021.
  19. Adriana C. Sanabria-Borbón, Nithyashankari Gummidipoondi Jayasankaran, Sanghoon Lee, Jiang Hu, Jeyavijayan Rajendran, and Edgar Sánchez-Sinencio. Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits, International Test Conference, pp. 1-10, 2020.
  20. Zhaokun Han, Muhammad Yasin, and Jeyavijayan Rajendran. Multi-Objective Strategies for Stripped-Functionality Logic Locking, IEEE International Symposium on Circuits and Systems, pp. 1-5, 2020.
  21. Zhaokun Han, Luciano Brignone, Austin Benedetti, Muhammad Yasin, and Jeyavijayan Rajendran. Protecting IC Supply Chain through Stripped-Functionality Logic Locking, in Government Microcircuit Applications & Critical Technology Conference, pp. 1-5, 2020.
  22. Muhammad Yasin, Chongzhi Zhao, Jeyavijayan Rajendran. SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis, in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-4. IEEE, 2019.
  23. Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Jason Fung, Arun Kanuparthi, Hareesh Khatri, Ahmad-Reza Sadeghi, and Jeyavijayan Rajendran. HardFails: Insights into Software-exploitable Hardware Bugs, in 28th {USENIX} Security Symposium, pp. 213-230. 2019.
  24. Nithyashankari Gummidipoondi Jayasankaran, Adriana Sanabria Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, and Jeyavijayan Rajendran. Breaking Analog Locking Techniques via Satisfiability Modulo Theories, in 2019 IEEE International Test Conference, pp. 1-10, 2019.
  25. Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, and Jiang Hu. Layout Recognition Attacks on Split Manufacturing, in the 24th Asia and South Pacific Design Automation Conference, pp. 45-50, 2019.
  26. Nithyashankari Jayasankaran, Adriana Sanabria, Jiang Hu, Edgar Sanchez-Sinencio, and Jeyavijayan J. V. Rajendran. Towards provably-secure analog and mixed-signal locking against overproduction, in International Conference on Computer-Aided Design, pp. 1-8. 2018.
  27. Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, and Jeyavijayan J. V. Rajendran. Towards provably-secure performance locking, in Design Automation and Test in Europe, 2018.
  28. M. Yasin, A. Sengupta, M. Ashraf, M. Nabeel, J. Rajendran, and O. Sinanoglu. Provably-secure Logic Locking: From Theory To Practice, in 2017 ACM SIGSAC Conference on Computer and Communications Security, pp. 1601-1618. 2017.
  29. M. Algappan, J. Rajendran, M. Doroslovacki, and G. Venkataramani. DFS Covert Channels on Multi-Core Platforms, in 2017 IFIP/IEEE International Conference on Very Large Scale Integration, pp. 1-6. IEEE, 2017.
  30. Y. Wang, T. Cao, J. Hu, and J. Rajendran. Front-End of Line Attacks in Split Manufacturing, in 2017 IEEE/ACM International Conference on Computer-Aided Design, pp. 1-8. IEEE, 2017.
  31. L. Feng, Y. Wang, W-K. Mak, J. Rajendran, J. Hu. Making Split Fabrication Synergistically Secure and Manufacturable, in 2017 IEEE/ACM International Conference on Computer-Aided Design, pp. 313-320. IEEE, 2017.
  32. M. Yasin, A. Sengupta, B. Schäfer, Y. Makris, O. Sinanoglu, J. Rajendran. What to Lock?: Functional and Parametric Locking, in ACM Great Lakes Symposium on VLSI, Pages 351-356, 2017.
  33. Y. Wang, J. Hu, and J. Rajendran. Routing perturbation for enhanced security in split manufacturing, in IEEE Asia and South Pacific Design Automation Conference, Pages 605-610, 2017.
  34. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran. Security analysis of Anti-SAT, in IEEE Asia and South Pacific Design Automation Conference, Pages 342-247, 2017.
  35. Md. B. Majumder, M. Uddin, J. Rajendran, and G. Rose. Sneak Path Enabled Authentication for Memristive Crossbar Memories, in IEEE Asian Hardware-Oriented Security and Trust Symposium, 2016.
  36. C. Yang, B. Liu, W. Wen, M. Barnell, Q. Wu, H. Li, Y. Chen, and J. Rajendran. Security of Neuromorphic Computing: Thwarting learning attacks using memristor’s obsolescence effect, in IEEE International Conference on Computer-Aided Design, Pages 97:1-97:6, 2016.
  37. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran. CamoPerturb: Secure IC Camouflaging for Minterm Protection, in IEEE International Conference on Computer-Aided Design, Pages 29:1-29:8, 2016.
  38. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran. SARLock: Resisting SAT attacks on Logic encryption, in IEEE Symposium on Hardware-Oriented Security and Trust, Pages 236-241, 2016.
  39. M. Bidmeshki, G. Reddy, L. Zhou, J. Rajendran, and Y. Makris. Hardware-based attacks to compromise the cryptographic security of an election system, in IEEE International Conference on Computer Design, Pages 153-156, 2016.
  40. A. Kanuparthi, J. Rajendran, and R. Karri. Controlling your control flow graph, in IEEE Symposium on Hardware-Oriented Security and Trust, Pages 43-48, 2016.
  41. Y. Wang, P. Chen, J. Hu, and J. Rajendran, The Cat and Mouse in Split Manufacturing, in IEEE/ACM Design Automation Conference, Pages 165:1-165:6, 2016.
  42. J. Tang, J. Rajendran, and R. Karri. Securing Pressure Measurements Using SensorPUFs, in IEEE International Symposium on Circuits and Systems, Pages 1330-1333, 2016.
  43. M. Yasin, S. Saeed, J. Rajendran, and O. Sinanoglu. Activation of Logic Encrypted Chips: Pre-Test or Post-Test?, in IEEE/ACM Design Automation and Test in Europe, Pages 139-144, 2016.
  44. J. Rajendran, A. M. Dhandayuthapany, V. Vedula, and R. Karri. Security Verification of 3rd Party Intellectual Property Cores for Information Leakage, in IEEE International Conference on VLSI Design, Pages 547-552, 2016.
  45. J. Rajendran, V. Vedula, and R. Karri. Detecting Malicious Modifications of Data in Third-Party Intellectual Property Cores, in IEEE/ACM Design Automation Conference, Pages 112:1–112:6, 2015.
  46. D. Shahrjerdi, J. Rajendran, S. Garg, R. Karri, and F. Koushanfar. Shielding and Securing Integrated Circuits using Sensors, in IEEE/ACM International Conference on Computer-Aided Design, Pages 170-174, 2014.
  47. D. Hoe, J. Rajendran, and R. Karri. Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors, in IEEE International Symposium on VLSI, Pages 516-521, 2014.
  48. A.Waksman, J. Rajendran, and S. Sethumadhavan. A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification, in 2014 51st ACM/EDAC/IEEE Design Automation Conference, pp. 1-4. IEEE, 2014.
  49. J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri. Security Analysis of Integrated Circuit Camouflaging, in ACM Conference on Computer and Communications Security, Pages 709-720, 2013. (Best Student Paper Award)
  50. M. Rostami, F. Koushanfar, J. Rajendran, and R. Karri. Hardware Security: Threat Models and Metrics, in IEEE Conference on Computer-Aided Design, Pages 819-823, 2013.
  51. C. Liu, J. Rajendran, C. Yang, and R. Karri. Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling, in IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Pages 101-106, 2013. (Best Student Paper Award)
  52. J. Rajendran, O. Sinanoglu, and R. Karri. VLSI Testing based Security Metric for IC Camouflaging, in IEEE International Test Conference, Pages 1-4, 2013.
  53. O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris. Reconciling the IC Test and Security Dichotomy, inIEEE European Test Symposium, Pages 1-6, 2013.
  54. J. Rajendran, H. Zhang, O. Sinanoglu, and R. Karri. High-Level Synthesis for Security and Trust, in IEEE International On-Line Testing Symposium, Pages 232-233, 2013.
  55. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, and R. Karri. A study on the effectiveness of Trojan detection techniques using a red team blue team approach, in IEEE VLSI Test Symposium, Pages 1-3, 2013.
  56. J. Rajendran, O. Sinanoglu, and R. Karri. Is Split Manufacturing secure?, in IEEE/ACM Design Automation and Test Conference, Pages 1259-1264, 2013.
  57. G. Rose, J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. Wysocki. Hardware Security Strategies Exploiting Nanoelectronic Circuits, in IEEE/ACM Asia and South Pacific Design Automation Conference, Pages 368-372, 2013.
  58. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri. Sneak Path Testing of Memristor-based Memories, in IEEE International Conference on VLSI Design, Pages 386-391, 2013.
  59. J. Rajendran, G. S. Rose, R. Karri, and M. Potkonjak. Nano-PPUF: A Memristor-based security primitive, in IEEE International Symposium on VLSI, Pages 84-87, 2012.
  60. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. Security Analysis of Logic Obfuscation, in IEEE/ACM Design Automation and Conference, Pages 83-89, 2012.
  61. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. Logic encryption: A fault analysis perspective, in IEEE/ACM Design Automation and Test in Europe, Pages 953-958, 2012.
  62. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. Applying IC Testing Concepts to Secure ICs, in GOMACTECH, 2012.
  63. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri. Engineering Crossbar based Emerging Memory Technologies, in IEEE International Conference on Computer Design, Pages 478-479, 2012.
  64. J. Rajendran, V.Jyothi, O.Sinanoglu, and R. Karri. Design and analysis of ring oscillator based Design for-Trust technique, in IEEE VLSI Test Symposium, Pages 105-110, 2011.
  65. J. Rajendran, V. Jyothi, and R. Karri. Blue team red team approach to hardware trust assessment: The embedded systems challenge experience, in IEEE International Symposium on Computer Design, Pages 285-288, 2011.
  66. J. Rajendran, R. Karri, and G.S. Rose. Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits, in IEEE International Symposium on Circuits and Systems, Pages 2241-2244, 2011.
  67. J. Rajendran, H. Manem, R. Karri and G.S. Rose. An Approach to Tolerate Process Related Variations in Memristor-based Applications, in IEEE Symposium on VLSI Design, Pages 18-23, 2011. (Best Student Paper Award)
  68. J. Rajendran, H. Manem, R. Karri and G.S. Rose. Memristor based Programmable Threshold Logic Array, in IEEE Symposium on Nanoscale Architectures, Pages 5-10, 2010.
  69. J. Rajendran, H. Borad, S. Mantravadi and R. Karri. SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers, in IEEE Symposium on Hardware Oriented Security and Trust, Pages 70-75, 2010.
  70. J. Rajendran, J. Jimenez, E. Gavas, V. Padman and R. Karri. Towards a comprehensive and systematic classification of hardware Trojans, in IEEE Symposium on Circuits and Systems, Pages 1871-1874, 2010.
  71. J. Rajendran, H. Manem and G.S. Rose. NDR based threshold logic fabric with memristive synapses, in IEEE-NANO, Pages 725-728, 2009.