LLMs for Agentic Hardware Design and Security

Course Description

(i) Basics of LLMs; (ii) LLMs in chip design; (iii) Fine-tuning LLMs through supervised fine-tuning and reinforcement learning for hardware design; (iv) LLM-based multi-agent systems for extended EDA tasks; (v) Verification and validation of LLM-based design; (vi) Benchmarking LLM functionality and reliability in the hardware design domain.

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Course Learning Outcomes

• Explain the fundamentals of large language models (LLMs) and their applications in hardware design.
• Develop prompt-based LLM frameworks for hardware design using prompt engineering, iterative feedback, and retrieval-augmented generation.
• Fine-tune LLMs on domain-specific datasets for Verilog generation using supervised fine-tuning and reinforcement learning.
• Develop LLM-based agents that complete multi-step hardware-design tasks, such as generating a processor design.
• Construct, evaluate, and optimize multi-agent workflows for extended hardware-design tasks across the electronic design automation (EDA) flow.

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Instructors

Prof. Jeyavijayan (JV) Rajendran
Prof. Jiang Hu
Prof. Paul Gratz